Scatter Gather DMA in Xilinx FPGA

Introduction

Naming convetion and System diagram

Register in Xilinx DMA IP

Scatter Gather Descriptor

  1. The descriptor is made up of eight 32-bit base words and 0 or 5 User Application words.
  2. The Buffer Length can describe up to 67,108,863 bytes of data buffer per descriptor.
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Descriptor Fields (Non-multichannel Mode)
Address Space Offset (1) Name Description
00h NXTDESC Next Descriptor Pointer
04h NXTDESC_MSB Upper 32 bits of Next Descriptor Pointer
08h BUFFER_ADDRESS Buffer Address
0Ch BUFFER_ADDRESS_MSB Upper 32 bits of Buffer Address.
10h RESERVED N/A
14h RESERVED N/A
18h CONTROL Control
1Ch STATUS Status
20h APP0 User Application Field 0 (2)
24h APP1 User Application Field 1
28h APP2 User Application Field 2
2Ch APP3 User Application Field 3
30h APP4 User Application Field 4

Data Structure for Scatter Gather Descriptor

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struct sg_bd{
unsigned int nxtdesc;//
unsigned int nxtdesc_msb;
unsigned int buf_addr; // address of the data to trasnfer from memory map to stream,
// should be aligned to the memory map data width
unsigned int buf_addr_msb;//
unsigned int reserved0;
unsigned int reserved1;
unsigned int ctrl; // 0x1c
unsigned int status;
unsigned int app0 ;
unsigned int app1 ;
unsigned int app2;
unsigned int app3;
unsigned int app4;
unsigned int dummy[3];
};

MM2S_CONTROL register (0x18h)

The value of thie register provides control for MM2S transfers from memory map to stream.

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Bits        Field Name                            Description
25 to 0 Buffer Length Indicates the size in bytes of the transfer buffer.
26 Transmit End Of Frame End of Frame. Flag indicating the last buffer to be processed.
• 0 = Not End of Frame.
• 1 = End of Frame.
27 TXSOF Start of Frame. Flag indicating the first buffer to be processed.