Xilinx FPGA Timing Constraint

Timing Constraint

Timing

Setup time:

Hold time:

Skew time:

Jitter

Timing Path

There are 4 timing path in FPGA: 2 intra-chip and 2 inter-chip path.

Path	Start point	End point	Constraint
Input port to the 1st register	ChipA/clk	RegA/D	set_input_delay
Path between registers	RegA/clk	RegB/D	create_clock
Last register to output port	RegB/clk	ChipB/D	set_output_delay
Input to output path	DinA	DinB	set_max_delay

Timing Model

Constraint on setup and hold time

I/O Constraint

PIN constraint

• PACKAGE_PIN: physical location of the pin
• IO_IOSTANDARD: voltage
• DIFF_TERM: Differential term

set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVCOMS18} [get_ports "led[0]"] 

Constraint on input and output

• set_input_delay and set_output_delay

Clock Constraint

1. create_clock

create_clock -name <name> -period <period> -waveform {<rise_time> <fall_time>} [get_ports <input_port>]

Clock used here must be primary clock: external clock or the RXOUTCLK/TXOUTCLK from Gigabyte Transceiver Gigabyte (GT). The timing unit in create_clock is ns and 50% duty cycle by default. Using the report_clocks, we can check the constraint is valid or not. In general, the clock input is differential. We only need to constrain the P termination. If both P and n are constrained, report_clock_interaction will be report unsafe. This will incur the memory overhead, increasing

After synthesize and implementation, use the following two methods to check the primary clock.

report_clock_networks -name mainclock
check_timing -override_defaults no_clock

2. create_generated_clock

3. set_clock_groups

• asynchronous

• multiple clock setting for the same clock network, -add

• BUFGMUX, apply mux to the input clocks.

4. Virtual Clock

Delay constraints for the I/O.

5. Max/Min delay constraint.